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| 1 introduction
table of contents 1.1 library description .............................................................................................. 1-1 1.2 features .............................................................................................................. 1-2 1.3 eda support ....................................................................................................... 1-4 1.4 product family..................................................................................................... 1-4 1.4.1 analog core cells...................................................................................... 1-4 1.4.2 internal macrocells .................................................................................... 1-12 1.4.3 compiled macrocells ................................................................................. 1-12 1.4.4 input/output cells ...................................................................................... 1-14 1.5 timings................................................................................................................ 1-16 1.6 delay model ........................................................................................................ 1-22 1.7 testability design methodology........................................................................... 1-24 1.8 maximum fanouts............................................................................................... 1-27 1.9 packages capability by lead count ................................................................... 1-34 1.10 power dissipation ............................................................................................. 1-36 1.11 v dd /v ss rules and guidelines .......................................................................... 1-39 1.12 crystal oscillator considerations...................................................................... 1-45 introduction 1.1 library description sec asic 1-1 std110 1.1 library description sec asic offers std110 as 0.25um cmos standard cell library. sec's 0.25um cell-based logic process providing up to 5 layers of interconnect metal with various i/o pad-pitch options such as 70um pitch pad and 80um pitch pad. std110 which reduced power dissipation and system cost by merging the logic and ips as a whole and connecting internally from logic to memory data bus is ideal for high-performance products such as graphics controller, projector, portable cd and so on. std110 can support up to eight million gate counts of logic providing 75% of usable gate. std110 is 25% faster than 0.35um library mdl90. logic density is 2.3 times greater than that of mdl90. the power consumption of compiled memory is 90% smaller than mdl90. std110 also supports fully user-configurable compiled memory and datapath elements. each element is provided as a compiler. two different types of compiled memories in std110 are available to support memories suitable to high-density and low-power applications. to support mixed voltage environments, 2.5v, 3.3v drive and 5v-tolerant io cells are available. lvttl, lvcmos, pci, osc, agp, pecl, hstl, lvds and usb buffers are supported. to better support a system-on-chip design style, various core cells are available including processor cores like arm7tdmi/arm9tdmi/ arm920t/arm940t from arm, teaklite and oak from dspg. the std110 supports data transmission and communication core such as usb, ieee1284 and uart. the list of analog core cells includes adc, dac, codec, lvds, ramdac and pll with various bits and frequency ranges. sec design methodology offers an comprehensive timing driven design flow including automated time budgeting, tight floorplan synthesis intergration, powerful timing analysis and timing driven layout. its advanced characterization flow provides accurate timing data and robust delay models for a 0.25um very deep-submicron technology. advanced verification methods like static timing analysis and formal verification provide an effective verification methodology with a variety of simulators and cycle based simulation. sec dft methodology supports scan design, bist and jtag boundary scan. sec provides a full set of test-ready ips with an efficient core test integration methodology. 1.2 features introduction std110 1-2 sec asic 1.2 features ? 2.5v standard cell library including processor and analog cores ? 0.25um ?ve layer metal(from four layer metal option) cmos technology - logic, processor and analog ? high basic cell usages - up to 8 million gates - maximum usage: 75% for ?ve layer metal ? high speed - typical 2-input nand gate delay (nd2d4): 70ps (f/o=2 + wl (0.02pf)) ? operation temperature (t a ) - commercial range: 0 c to +70 c - industrial range: - 40 c to +85 c ? digital cores usages - hard-macro: arm7tdmi, arm9tdmi, arm920t, arm940t, oak, teaklite - soft-macro: amba, dma controller, sdram controller, interrupt controller, iic, wdt, rtc, usb, irda, uart(16c450, 16c550), fast ethernet mac, p1394a link, rs decoder, viterbi decoder ? analog cores usages - ultra low voltage analog core (2.5v and 1.8v) available - analog core supply voltage: 2.5v analog core: 2.5v 5% 1.8v analog core: 1.8v 5% - adc: 8bit (30m, 2.5v), 10bit ((30m, 100m, 2.5v), (250k, 20m, 1.8v)), 12bit (200k, 20m, 2.5v) - dac: 8bit (2m, 2.5v), 10bit ((300m, 2.5v), (2m, 1.8v)), 12bit ((2m, 2.5v), (80m, 1.8v)) - codec: 8bit (8k~11k), 16bit (44.1k) - pll: 25m ~ 300m (fspll, 2.5v), 1g (pll, 1.8v), 20m ~ 170m(fspll, 1.8v) - others: 300m (ramdac+pll) ? fully user-con?gurable static rams and roms - high-density and low-power memory available - duty-free cycle in synchronous memory available - 2-bank architecture available - flexible aspect ratio available - up to 256k-bit single-port sram available. - up to 128k-bit dual-port sram available. - up to 512k-bit diffusion and metal-2 rom available. - up to 16k-bit multi-port register ?le available. - up to 32k-bit fifo available. ? fully con?gurable datapath macrocells - 4 ~ 64 bit adder available - 4 ~ 64 bit barrel shifter available - 6 ~ 64 bit multiplier with 1-stage pipeline available - various output driver strength available - a tightly integrate apollo, avant!, design environment ? i/o cells - 2.5v/3.3v and 5v tolerant io - 3-level (high, medium, no) slew rate control - 1/2/4/6/8/10/12ma available for 3.3v and 2.5v output buffers - 1/2/3ma available for 5v-tolerant output buffers introduction 1.2 features sec asic 1-3 std110 ? io ip available - pci ((33mhz, 66mhz, 3.3v), (33mhz, 3.3/5v tolerant)) - usb (full speed/low speed) - sstl2 (ddr sdram interface, up to 200mhz) - agp (agp2.0 compliant, 66mhz@1x,133mhz@2x, 266mhz@4x) - pecl (2.5v interface, up to 400mhz) - hstl (class1, class2, 30mhz) - lvds (3.3v(2.5v optional) interface, 300mhz) ? various package options - qfp, thin qfp, power qfp, plastic bga, super bga, plastic leaded chip carrier, etc. ? fully integrated cad software and eda support - logic synthesis: synopsys design compiler - logic simulation: cadence verilog-xl, cadence nc-verilog, viewlogic viewsim, mentor modelsim-vhdl, mentor modelsim-verilog, synopsys vss, synopsys vcs - scan insertion and atpg: synopsys testgen, synopsys test compiler, mentor fastscan - static timing analysis: synopsys primetime, synopsys motive - rc analysis: avant! star-rc - power analysis: synopsys designpower, cubicpower (ln-house tool) - formal veri?cation: synopsys formality, chrysalis design verifyer, verplex tuxedo-lec - fault simulation: cadence verifault, supertest (in-house tool) - delay calculator: cubicdelay (in-house tool) ? std110 contains 12 user selectable clock tree cells(ctc). at the pre-layout design stage, these will be used as the cells which represent actual clock tree informatin of p&r. the key features of new sec asic cts ?ow are as fol- lows: - 12 user selectable clock tree cells(ctc) for std110 - good pre-layout and post-layout correlation - no customer netlist modi?cation - accurate post-layout back-annotation mechanism - insertion delay, skew, transition time management - clock tree information ?le generation - cover 100 to 30,000 fanouts and up to 1m gate count for cts spanning block (gccsb) - tightly coupled with sec in-house delay calculator, cubicdelay gated cts support - hierarchical/flatten verilog, edif interface for p&r for more detail information for ctc flow, refer to ctc flow guideline for cubicdelay included in sec asic design kit. 1.3 eda support introduction std110 1-4 sec asic 1.3 eda support sec asic provides an efficient solution for multi-million gate asics in very deep submicron (vdsm) technology. for large system-on-chip (soc) type designs, static verification methodology (static timing analysis and formal verification) will shorten your design cycle time, which in turn will lessen today's ever-increasing time-to-market pressure. our design-for-test (dft) methodology and service take you through all phases of test insertion, test pattern generation and fault grading to get high test coverage. std110 supports a rich collection of industry-standard eda tools from cadence, synopsys, mentor graphics, and avant! on multiple design platforms such as solaris and hp. customers are allowed to choose among the industry-leading eda tools from design capture, synthesis, simulation, and dft to layout. several powerful proprietary software tools are seamlessly integrated in our design kits to improve your product quality. for high simulation accuracy, std110 uses a proprietary delay calculator. cell delay is calculated based on a matrix of delay parameters for each macrocell, and signal interconnect delay is calculated based on the rc tree analysis. 1.4 product family std110 library include the following design elements: n analog core cells n digital core cells n internal macrocells n compiled macrocells n input/output cells. 1.4.1 analog core cells introduction to analog cores sec asic is one of the leading suppliers of cell based mixed analog and digital designs. as a leading supplier of mixed analog and digital designs, sec asic has more analog design experience than any other vendors. analog has been and will continue to be a part of the strategic focus at sec asic. analog design is a part of the total sec asic integrated design system. workstation symbols are supplied for analog cells and are entered as part of the design by the customer or design center. sec asic uses basically the same automatic layout and verification tools for analog cells as for digital cells. analog designs are processed on the same production line as digital designs. sec's analog core family comprises adc,dac,pll and sigma-delta adc/dac, and their brief functional descriptions are introduced below. [data sheets for all analog cores available] analog-to-digital converters analog-to-digital converters provide the link between the analog world and digital systems. due to their extensive use of analog and mixed analog-digital operations, a/d converters often appear as the bottleneck in data processing applications, limiting the overall speed or precision. an a/d converter produces a digital output, d, as a function of the analog input, a: d = f(a) while the input can assume an infinite number of values, the output can be selected from only a finite set of codes given by the converter's output word length(i.e, resolution). thus, the adc must approximate each input level with one of these codes, this process is so called 'quantization'. introduction 1.4 product family sec asic 1-5 std110 in a digital system the amplitude is quantized into discrete steps, and at the same time the signal is sampled at discrete time intervals. this time interval is called sampling time or sampling frequency. after sampling and quantization process, the analog signal(a) becomes digital output (d). digital-to-analog converters the d/a converters are the digital-to-analog conversion circuits, which are also called dacs. they can be considered as decoding devices that accept digitally coded signals and provide analog output in the form of currents or voltages. in this manner, they provide an interface between the digital signal of the computer systems and continuous signals of analog world. they are employed in a variety of applications, from crt display systems and voice sythesizers to automatic test systems, digital controlled attenuators, and process control actuators. in addition, they are key components inside most a/d converters. figure 1 shows the functional block diagram of a basic d/a converter system. the input to the d/a converter is a digital word, made up a stream of binary bits comprised of 1's and 0's. the output analog quantity a, which can be a voltage or current, is related to the input as where k is a scale factor, v ref is a reference voltage, n is the total number of bits, and b1,b2,...,bn are the bit coefficients, which are quntized to be a 1 or a 0. as a function of the input binary word which determines the bit coefficients, the output exhibits 2 n discrete voltage level ranging from zero to a maximum value of with a minimum step change d vo given as \ figure 1-1. functional block diagram of basic d/a converter akv ref b 1 2 1 ------ b 2 2 2 ------ ? bn 2 n ----- - +++ = vo(max) v ref 2 n 1 C 2 n ------------- = d vo v ref 2 n ------------- = d/a converter b1 b2 b3 bn analog output digital data input 1.4 product family introduction std110 1-6 sec asic sigma-delta adc/dac vlsi offers high speed and high density, but reduced accuracy for analog components and reduced signal range (reduced dynamic range). hence, an exchange of digital complexity and of resolution in time for resolution in signal amplitude is needed. so good solution is over-sampling data converter. oversampling sigma-delta converter is used in slow speed (audio band) application because of process limit. it's noise shaping (sigma-delta) feature make high resolution about max. snd=90~100db in adc path, analog single input is converted to differential signal with anti-alias- ing filtering through anti-aliasing filter block. and sigma-delta modulator converts the signal into oversampled noise-shaping 1bit pdm (pulse density modulation). following digital decimation filter reject the out of band noise and outputs 16bits high resolution digital data with down sampled to fs rate. in dac path, digital in- put data is oversampled by interpolation filter and it is converted to noise-shaped 1bit pdm through digital sigma-delta modulator. analog sc-post-filter rejects the out of band noise. and anti-image filter rejects sampling images and outputs sin- gle analog signal with high resolution. phase locked loop samsungs pll cores implemented as an analog function provide frequency multiplication capabilities and enable system designers to synchronize asic chip-level clock networks with a common reference signal. in the past, designers wishing to incorporate a pll into a digital design environment had only two options: (1) a special mixed-signal process to incorporate analog functions onto the chip (2) an all digital pll that can be incorporated into a standard digital process. however, a mixed-signal process is too expensive to be a feasible solution. on the other hand digital plls typically require huge silicon area and exhibits poor locking time despite their high accuracy. differing from the previous solutions, samsung's pll cores can be implemented on standard digital cmos process while functioning as an analog pll. samsung's pll cores: * require only a few off-chip passive components for the whole function * remove the need for an expensive mixed-signal process * provide faster locking time than all digital plls * present low jitter characteristics glossary by core families 1. digital-to-analog converter 1. resolution - an n-bit binary converter should be able to provide 2 n distinct and different analog output values corresponding to the set of n-bit binary words. a converter that satisfies this criterion is said to have resolution of n bits. the smallest output change that can be resolved by a linear dac is 2 -n of the full-scale span. 2. accuracy - error of a d/a converter is the difference between the actual analog output and the output that is expected when a given digital code is applied to the converter. source of error include gain error, offset error, linearity errors and noise. error is usually commensurate with resolution, less than 2 -(n+1) , or 1/2 lsb of full scale. introduction 1.4 product family sec asic 1-7 std110 figure 1-2. error of d/a converter 3. lsb (least-significant bit) - in a system in which a numerical magnitude is represented by a series of binary digits, the lsb is that bit that carries the smallest value or weight. it represents the smallest analog change that can be resolved by an n-bit converter. lsb (analog value) = fsr/2 n fsr = full-scale range, n = number of bits 4. msb (most-significant bit) - the binary digit with the largest numerical weighting. normally, the msb of a digital word has a weighting of 1/2 the full range. 5. compliance-voltage range - for a current output dac, the maximum range of(output) terminal voltage for which the device will provide the specified current- output characteristics. 6. glitch - a glitch is a switching transient appearing in the output during a code transition. its value is expressed as a product of voltage (v*ns) or current (ma*ns) and time duration or charge transferred. 7. harmonic distortion (and total harmonic distortion) - the dac is driven by the digitized representation of sine wave. the ratio of the rms sum of the harmonics of the dac output to the fundamental value is the thd. usually only the lower order harmonics are included, such as second through fifth. v1: rms amplitude of the fundamental 8. signal-to-noise ratio (snr) - this signal to noise ratio depends on the resolution of the converter and automatically includes specifications of linearity, distortion, sampling time uncertainty, glitches, noise, and settling time. over half the sampling frequency, this signal to noise ratio must be specified and should ideally follows the theoretical formula; s/n max = 6.02n + 1.76db 9. slew rate - slew rate of a device or circuit is a limitation in the rate of change of output voltage, usually imposed by some basic circuit consideration such as limited current to charge of capacitor. amplifiers with slew rate of a few v/ m s are common and moderate in cost. slew rates greater than about 75 v/ m s are usually seen only in more sophisticated (and expensive) devices the output slewing speed of a voltage-output d/a converter is usually limited by the slew rate of the amplifier used at its output (if one is used). offset error ideal actual analog output digital input analog output digital input ideal actual gain error thd 20 v 2 2 v 3 2 v 4 2 v 5 2 +++ () 12 v 1 -------------------------------------------------------------- - log = 1.4 product family introduction std110 1-8 sec asic 10. settling time - the time required, following a prescribed data change from the 50% point of the login input change, for the output of a dac to reach and to remain within a given fraction (usually 1/2lsb) of the final value. typical pre- scribed changes are full scale, 1msb and 1lsb at a major carry. settling time of current-output dacs is quite fast. the major share of settling time of a voltage- output dac is usually contributed by the settling time of the output op-amp circuit. figure 1-3. setting time 11. power-supply sensitivity -the sensitivity of a converter to changes in the power-supply voltages is normally expressed in terms of percent-of-full-scale change in analog output value (of fractions of 1lsb) for a 1% dc change in the power supply. power supply sensitivity may also expressed in relation to a specified dc shift of supply voltage. a converter may be considered "good" if the change in reading at full scale does not exceed 1/2lsb for 3% change in power supply. even better specs are necessary for converters designed for battery operation. 12. ile (integral linearity error) - linearity error of a converter, expressed in %, ppm of full-scale range or multiples of 1lsb, is a deviation of the analog values in a plot of the measured conversion relationship from a straight line. the straight line can be either a "best straight line" determined empirically by manipulation of the gain and/or offset to equalize maximum positive and negative deviation of the actual transfer characteristics from this straight line; or it can be a straight line passing through the endpoints of the transfer characteristic endpoints of the transfer characteristic after they have been calibrated (sometimes referred to as "endpoint" linearity). endpoint linearity error is similar to relative accuracy error. for multiplying d/a converters, the analog linearity error, at a specified digital code, is defined in the same way as for multipliers, by deviation from a "best straight line" through the plot of the analog output-input response. 13. dle (differential linearity error) - any two adjacent digital codes should re- sult in measured output values that are exactly 1lsb apart (2-n of full scale for an n-bit converter). any deviation of the measured "step" from the ideal difference is called differential linearity error expressed in multiplies of 1lsb. it is an important specification because a differential linearity error greater than 1lsb can lead to non-monotonic response in a d/a converter and missed codes in an a/d convert- er. 14. monotonic - a dac is said to be monotonic if the output either increases or remains constant as the digital input increases with the result that the output will always be a single-valued function of the input. the specification "monotonic" final setting v 0 +d v 0 1 slewing setting time to d v 0 -d v 0 slew rate introduction 1.4 product family sec asic 1-9 std110 (over a given temperature range) is sometimes substituted for a differential non- linearity specification since differential nonlinearity less than 1lsb is a sufficient condition for monotonic behaviour. 2. analog-to-digital converter 1. ile (integral linearity error: inl) - integral nonlinearity refers to the deviation of each individual code from a line drawn from "zero" through "full scale". the point used as "zero" occurs 1 / 2 lsb before the first code transition. "full scale" is defined as a level 1 1 / 2 lsb beyond the last code transition. the deviation is measured from the center of each particular code to the true straight line. 2. dle (differential linearity error: dnl) - an ideal adc exhibits code transitions that are exactly 1lsb apart. dnl is the deviation from this ideal value. it is often specified in terms of the resolution for which no missing codes are guaranteed. 3. offset error - the first transition should occur at a level 1/2lsb above "zero". offset is defined as the deviation of the actual first code transition from that point. 4. gain error - the first code transition should occur for an analog value 1/2lsb above nominal negative full scale. the last transition should occur for an analog value 1 1 / 2 lsb below the nominal positive full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. 5. pipeline delay (latency) - the number of clock cycles between conversion initiation and the associated output data being made available. new output data is provided every clock cycle. 6. effective number of bits (enob) - this is a measure of a device's dynamic performance and may be obtained from the sndr or from a sine wave curve test fit according to the following expression: enob = sndr - 1.76/6.02 enob = n-log2[rms error (actual) / rms error (ideal)] 7. analog bandwidth - the analog input frequency at which the spectral power of the fundamental frequency, as determined by fft analysis is reduced by 3db. 8. aperture delay - the delay between the sampling clock and the instant the analog input signal is sampled. 9. aperture jitter - the sample to sample variation in aperture delay. 10. bit error rate (ber) - the number of spurious code errors produced for any given input sine wave frequency at a given clock frequency. in this case it is the number of codes occurring outside the histogram cusp for a 1/2 fs sine wave. 11. signal to noise ratio - this signal to noise ratio depends on the resolution of the converter and automatically includes specifications of linearity, distortion, sampling time uncertainty, glitches, noise, and settling time. over half the sampling frequency, this signal to noise ratio must be specified and should ideally follow the theoretical formula; s/n max = 6.02n + 1.76db 1.4 product family introduction std110 1-10 sec asic 3. phase locked loop 1. lock time - the time it takes the pll to lock onto the system clock. fast or slow lock time may be controlled by the loop filter characteristics. the loop filter characteristics are controlled by varying the r and c components. (remember that r and c define the damping-factor as well) 2. phase error - the phase difference between the feedback clock signal and the system signal clock. 3. clock jitter - the deviations in a clock's output transitions from their ideal positions define the clock jitter. jitter is sometimes specified as an absolute value in nanoseconds. all jitter measurement are made at a specified voltage. 1) cycle-to-cycle jitter: the change in a clock's output transition from its corresponding position in the previous cycle. this kind of jitter is the most difficult to measure and usually requires a time-interval analyzer figure 1-4. cycle-to-cycle jitter : the maximum of such values over multiple cycles (j1,j2...) is the max. cycle-to- cycle jitter. 2) period jitter: period jitter measures the maximum change in a clock's output transition from its ideal position. you can use period-jitter measurements to calculate timing margins in systems. figure 1-5. period jitter 3) long-term jitter: long-term jitter measures the maximum change in a clock's output transition from its ideal position over many cycles. how many cycles depends on the application and the frequency. a classic example of system affected by long-term jitter is a graphics card driving a crt 4) power down mode: pll state in which the quiescent current is lowered to a very low level to conserve power. 5) synthesize clock: a system clock may run at a relatively low rate compared to system components. a cpu, for example, may require an internal clock that is several times faster than the system i/o bus clock. designers can use pll clock t1 t2 t3 noise: jitter j1 = t2 - t1 jitter j2 = t3 - t2 clock ideal cycle: t1 jitter introduction 1.4 product family sec asic 1-11 std110 technology to synthesize a higher frequency on-chip clock using the system clock as a reference. 6) deskew clock: multiple chips on a printed circuit board or cores of different sizes within a single system on a chip experience clock skew. by using pll or dll technology to shift the phase of the reference clock within each chip or core, designers can minimize skew tune a system to perform up its potential. 7) duty ratio: the percentage of the period that the output is in a high state. 8) output frequency range: the maximum output frequency range minus the minimum output frequency that is produced with an input signal for which the cell specifications still apply. customer service sec provides a full custom support for our customers need of analog cores. sec's worldwide sales offices and representatives give our customers a first- hand support for analog cores. and if needed, sec engineers are prepared to provide a fully customized total solution to satisfy our customers. technical support if our customers want to develop mixed-signal products, sec provides all techni- cal support to meet customers needs. mixed-signal design is quite different from pure logic design in terms of circuit design, techniques, layout and test method- ology. thus sec provides a successful technical guide and firmly support for all development steps. de?nition of analog core data sheet types each product developed by sec will be supported by technical literature where the data sheets progress through the following levels of refinement 1. core preview describes the main features and specifications for core that is under development. some specifications such as exact pin-outs may not be finalized at time of publication.the purpose of this document is to provide customers with advance product planning information. 2. preliminary datasheet this is the first document completely describing a new core. it contains an features, application, timing diagram, theory of operation, core pin information, test guide, layout guide and ac/dc electrical information. this data sheet are based on prototype silicon performance and on worst case simulation models.the purpose of this data sheet is to provide asic customer with technical information sufficiently detailed to guarantee that they can safely begin active development. 3.final data sheet this is an updated version of preliminary data sheet reflecting actual performance of the final silicon. updates include tighter specifications, more min. and max. values. the purpose of this data sheet is to communicate the confirmed performance of cores which have passed qualification, been fully characterized. 1.4 product family introduction std110 1-12 sec asic 1.4.2 internal macrocells internal macrocells are the lowest level of logic functions such as nand, nor and ?ip-?op used for logic designs. there are about 471 different types of internal macrocells. they usually come in four levels of drive strength (0.5x, 1x, 2x and 4x). these macrocells have many levels of representationslogic symbol, logic model, timing model, transistor schematic, hspice netlist, physical layout, and placement and routing model. 1.4.3 compiled macrocells compiled macrocells of std110 consist of compiled memory and compiled datapath macrocells. 1.4.3.1 compiled memory macrocells memories in std110 are fully user-configurable and are provided as a compiler. two different types of memories are available in std110. one is suitable for high- density application with high-performance, called std110-hd compiled memory. the other is suitable for low-power application, called std110-lp compiled memory. in std110-hd compiled memory, eight types of memories are available such as single-port synchronous/asynchronous static ram, dual-port synchronous static ram, synchronous diffusion/metal-programmable rom, multi-port asynchronous register file and synchronous first-in first-out memory. synchronous memories have a fully synchronous operation at the rising-edge of clock and the duty-free cycle is available. also, the bit-write capability is available. asynchronous memories have a synchronous operation for a write enable signal during write mode and have an asynchronous operation for address signal during read mode. multi-port asynchronous register file supports four kinds of configurations such as 2 port(1-read/1-write), 3 port(1-read/2-write and 2-read/1- write) and 4 port (2-read/2-write). the first-in first-out memory which is widely used in communication buffering types of applications has also fully synchronous operation at the rising- edge of clock. on the other hand, in std110-lp compiled memory, five types of memories are available such as single-port synchronous/asynchronous static ram, dual-port synchronous static ram and synchronous diffusion/metal-programmable rom. synchronous memories are almost same as that of std110-hd except that the duty-free cycle is not available. asynchronous memory is same as that of std110-hd. to dramatically reduce the power consumption in std110-lp, some of low- power techniques such as a partial activation architecture in cell array and a divided word-line structure was adopted, rather than std110-hd. basically in std110-hd and std110-lp, the power-down mode which significantly reduces the power dissipated during a read or write mode is provided. also compiled memories have a standby mode except multi-port asynchronous register file and first-in first-out memory. while in standby mode, the data stored in the memory is retained, data outputs remain stable and the power is greatly reduced because memory operation is internally blocked while the memory contents and the data outputs are unaffected. introduction 1.4 product family sec asic 1-13 std110 to improve the memory performance and to reduce the power consumption, 2- bank architecture is provided except some memories such as dual-port synchronous static ram, multi- port asynchronous register file and first-in first-out memory. in 2-bank architecture, only one bank is activated and the other bank is in standby mode. to support various memory shapes which are determined by the floorplan of a chip design, flexible memory aspect ratios are provided. for certain specific memory configuration, all types of timing, power and area values are provided by an automatic datasheet generator. to easily do interface to layout, the physical abstract data for silicon ensemble and apollo, called phantom cell or black box, is provided. bist(built-in self-test) circuitry is currently available for most of std110 compiled memories. bist circuits are designed to detect a set of fault types that impact the functionality of memory and is generated by a softmacro-based bist generator. the softmacro-based bist generator generates both an individual bist netlist for each memory and a shared bist netlist for all memories used in a design. however, when several memories of the same or the different type area used in the design, if you generate the individual bist netlist for each memory, there are some redundant blocks because the individual bist netlist has same function. in this case, it would better use the shared bist netlist to eliminate such redundancy and reduce area. 1.4.3.2 compiled datapath macrocells compiled datapath macro cells include adder, barrel shifter and multiplier. adder performs the adding or adding/subtracting operation on the control of a mode selection signal. barrel shifter makes input data shift or rotate in the left/right direction. in the shift operation, the vacant bit can be padded with zero, msb value, or external data. multiplier performs the 2's compliment multiplication. one pipeline stage insertion is available to get a high operating frequency. they have two output drive strengths, which are equal to the 1x and 2x-drive in the primitive cell library. the hard macro cells are built through the apollo, placement and routing tool from avant!. all the leaf cells have the same physical configuration compatible with the primitive cell library. it allows that any primitive cell can be used as a bit slice cell in the datapath module design. we provide two kinds of engineering design services. one is to support additional compiled datapath macrocells such as alus, comparators, priority encoders, incrementers and decrementers, and so on. another is to make hardwired datapath module design which provides a regular structured layout. 1.4 product family introduction std110 1-14 sec asic 1.4.4 input/output cells there are about seven hundreds different i/o buffers. each i/o cell is implemented solely on the basic i/o cell architecture which forms the periphery of a chip. a test logic is provided to enable the efficient parametric (threshold voltage) testing on input buffers including lvcmos and ttl level converters, schmitt trigger input buffers, clock drivers and oscillator buffers. pull-up and pull-down resistors are optional features. three basic types of output buffers (non-inverting, tri-state and open drain) are available in a range of driving capabilities from 1ma to 12ma for 2.5v, 3.3v drive and from 1ma to 3ma for 5.0v tolerant drive. one or two levels of slew rate controls are provided for each buffer type (except 1ma, 2ma and 3ma buffers) to reduce output power/ground noise and signal ringing, especially in simultaneous switching outputs. bi-directional buffers are combinations of input buffers and output buffers (tri- state and open drain) in a single unit. the i/o structure has been fully characterized for esd protection and latch-up resistance. for user's convenience, std110 library provides 100k w pull-down and pull-up resistance respectively. 1.4.4.1 i/o applications to support mixed voltage environments, lvttl, lvcmos and schmitt trigger i/ o cells are available at 2.5v, 3.3v interface and 5v tolerant interface. the i/o application diagram is as follows. figure 1-6. i/o applications 1.4.4.2 i/o cell drives options to provide designers with the greater flexibility, each i/o buffer can be selected among various current levels (e.g., 1ma, 2ma,..., 12ma). the choice of current- level for i/o buffers affects their propagation delay and current noise. the slew rate control helps decrease the system noise and output signal overshoot/undershoot caused by the switching of output buffers. the output edge rate can be slowed down by selecting the high slew rate control cells. 2.5v b t d 3.3v b t d 2.5 3.3 2.5v c s 3.3v c s t internal circuit operating voltage: 2.5v 2.5 3.3/ input buffer output buffer 5v tolerant introduction 1.4 product family sec asic 1-15 std110 std110 provides three different sets of output slew rate controls. only one i/o slot is required for any slew rate control options. 1.4.4.3 5v tolerant i/o buffers std110 i/o library is based on a process which has the most optimum performance in 2.5v. in this process, voltage more than 3.6v are not allowed at the gate oxide because of a reliability problem. and a special circuit is adopted in order to make pin voltage tolerable up to 5.25v and to offer ttl interface driving up to 3ma. obviously, this circuit is constructed not to permit more than 3.6v at the gate oxide. the external circuit diagram is as follows. the maximum external tolerance of this buffer is 5.25v. it can be used as a 3.3v normal buffer. figure 1-7. 5v tolerant i/o buffers 1.4.4.4 pci buffers pci buffers are designed for pci local bus application which is an industry- standard, high-performance 32bit or 64bit bus architecture. sec asic offers input, output, bi-directional pci buffers for 33mhz and 66mhz operation. these buffers are compliant with pci local bus speci?cation 2.1. 1.4.4.5 usb (universal serial bus) buffers various kinds of peripheral equipment such as mouse, joy stick, keyboard, modem, scanner and printer improve the power of a computer. however, it is not easy to connect and use them properly in the computer. usb speci?cation established late in 1995 is a good solution for this problem, providing facile method of an expansion. sec asic offers full speed and low speed usb buffers that complies with universal serial bus speci?cation 1.0, 1.1. 1.4.4.6 other buffers sec asic can support various kinds of buffers such as hstl, sstl, agp, pecl, lvds, and so on. for more information please contact us. 3.3v 3.3v 5.0v output voltage open drain output 5v tolerant input tri-state output bi-directional i/o 0.25 m m 2.5v process normal 5v process 3.3v ttl input ttl input 1.5 timings introduction std110 1-16 sec asic 1.5 timings 1.5.1 wire length load table 1-1. shows the equivalent standard load matrix for 4-layer and 5-layer metal interconnect. the equivalent standard load values are function of gate count and fanout. these values are based on capacitive loading and are used in wire length estimates which affect propagation delay. table 1-1. equivalent standard loads for 4-layer and 5-layer metal interconnect gates count fanouts 1 2 3 4 5 6 7 8 16 32 64 4lm 5000 1.159 2.242 3.822 5.113 5.965 7.020 7.859 10.94 28.672 45.642 79.821 10000 1.530 2.932 5.561 7.701 8.964 10.500 12.110 15.211 29.903 47.725 83.520 50000 4.192 8.247 12.439 16.494 16.801 17.980 21.026 22.806 35.536 48.347 84.605 100000 4.596 9.327 13.925 18.523 18.889 20.241 23.582 27.031 41.002 54.253 94.944 150000 12.843 17.125 21.406 22.684 23.600 24.296 26.001 29.730 39.828 63.672 127.344 200000 13.520 18.026 22.533 23.885 24.849 25.582 27.372 31.299 41.865 66.931 133.812 300000 14.871 19.830 24.786 26.588 27.596 28.363 30.317 34.634 46.268 73.871 147.587 400000 16.225 21.631 26.852 28.693 29.845 30.718 32.868 37.479 50.016 79.707 159.207 500000 18.099 24.132 30.166 32.177 33.435 34.390 36.777 42.032 53.235 84.861 169.459 600000 19.375 25.836 32.476 34.593 35.915 36.919 39.467 45.186 54.763 87.312 174.320 800000 22.324 29.767 37.739 40.113 41.593 42.719 45.642 52.399 59.180 94.390 188.385 1000000 25.078 33.439 42.657 45.272 46.898 48.140 51.408 59.135 63.283 100.964 201.447 1500000 32.631 43.509 56.047 59.341 61.381 62.946 67.174 77.514 75.639 120.743 240.788 2000000 39.706 52.941 68.596 72.524 74.956 76.821 81.946 94.736 87.196 139.244 277.587 2500000 46.327 61.770 80.342 84.864 87.657 89.807 95.771 110.853 97.994 156.527 311.959 3000000 52.517 70.023 91.321 96.399 99.532 101.946 108.693 125.919 108.065 172.646 344.022 4000000 60.251 80.335 104.770 110.594 114.189 116.958 124.701 144.463 123.979 198.073 394.685 5000000 67.558 90.078 117.479 124.008 128.041 131.146 139.827 161.985 139.017 222.099 442.560 6000000 75.754 101.005 131.728 139.052 143.573 147.053 156.788 181.634 155.879 249.038 496.241 5lm 5000 1.101 2.131 3.631 4.856 5.667 6.669 7.466 10.397 27.238 43.360 75.830 10000 1.454 2.786 5.283 7.317 8.515 9.976 11.505 14.451 28.408 45.339 79.344 50000 3.982 7.834 11.818 15.670 15.961 17.081 19.976 21.666 33.760 45.929 80.374 100000 4.366 8.861 13.229 17.597 17.944 19.229 22.403 25.679 38.952 51.540 90.198 150000 12.201 16.268 20.336 21.549 22.420 23.081 24.701 28.244 37.837 60.488 120.977 200000 12.843 17.125 21.406 22.691 23.606 24.304 26.004 29.734 39.771 63.584 127.122 300000 14.128 18.839 23.546 25.259 26.216 26.944 28.801 32.903 43.955 70.178 140.207 400000 15.414 20.549 25.509 27.257 28.353 29.181 31.225 35.606 47.515 75.722 151.247 500000 17.195 22.925 28.658 30.567 31.763 32.670 34.938 39.931 50.573 80.618 160.986 600000 18.406 24.543 30.852 32.862 34.119 35.073 37.494 42.926 52.025 82.947 165.605 800000 21.208 28.278 35.852 38.107 39.514 40.584 43.360 49.779 56.220 89.670 178.967 1000000 23.825 31.767 40.524 43.008 44.554 45.733 48.837 56.178 60.119 95.916 191.374 1500000 31.000 41.333 53.245 56.374 58.312 59.798 63.815 73.637 71.856 114.706 228.749 2000000 37.721 50.295 65.166 68.898 71.208 72.980 77.849 90.000 82.837 132.281 263.707 2500000 44.011 58.682 76.324 80.621 83.274 85.317 90.983 105.311 93.093 148.700 296.362 3000000 49.891 66.523 86.755 91.579 94.555 96.849 103.257 119.622 102.661 164.014 326.821 4000000 57.239 76.318 99.532 105.065 108.479 111.110 118.466 137.239 117.779 188.169 374.950 5000000 64.180 85.575 111.606 117.807 121.639 124.588 132.836 153.885 132.067 210.995 420.432 6000000 71.965 95.955 125.141 132.099 136.394 139.700 148.949 172.552 148.084 236.587 471.429 7000000 78.436 104.582 136.393 143.976 148.655 152.259 162.339 188.067 161.397 257.858 513.812 8000000 87.950 117.266 152.935 161.439 166.687 170.727 182.031 210.877 180.976 289.134 576.135 introduction 1.5 timings sec asic 1-17 std110 1.5.2 timing parameters this section discusses issues involving timing parameters. 1.5.2.1 transition time figure 1-8. shows the definition of rise transition time (t r ) and fall transition time (t f ). transition time is de?ned as the delay between the time when the input (out- put) signal voltage level is 10% of supply voltage (v dd ) and the time of the input (output) signal voltage level is 90% of v dd . figure 1-8. rise and fall transition times 1.5.2.2 propagation delays figure 1-9. shows the definition of propagation delays. propagation delay is de- fined as the delay between the time when the input signal voltage level is 50% of supply voltage (v dd ) and the time when the output signal voltage level is 50% of v dd . figure 1-9. propagation delay t r t f 10% 90% 90% 10% v dd 50% 50% t plh 50% 50% t plh 50% 50% t phl 50% 50% t phl v dd in out in in out out in out 1.5 timings introduction std110 1-18 sec asic 1.5.2.3 setup / hold time figure 1-10. shows the definition of setup time and hold time. the setup timing check is defined as the minimum interval which a data signal must remain stable before active transition of a clock. any change to the data signal within this inter- val results in a timing violation. the hold timing check is defined as the minimum interval which a data signal must remain stable after active transition of a clock. any change to the data signal with- in this interval results in a timing violation. figure 1-10. setup and hold times 1.5.2.4 recovery times figure 1-11. shows the definition of recovery time. a recovery timing check meas- ures the time between the release of an asynchronous control signal from the ac- tive state to the next active clock edge. for example, the time between rn and the ck of fd2 cell. if the active edge of the ck occurs too soon after the release of the rn, the state of the fd2 becomes uncertain. the state can be the value set by the rn or the value clocked into the fd2 from the data input. figure 1-11. recovery time d ck t su t hd 50% 50% 50% rn ck t rc 50% 50% introduction 1.5 timings sec asic 1-19 std110 1.5.2.5 removal times figure 1-12. shows the definition of removal time. a removal timing check meas- ures the time between the active clock edge and the release of an asynchronous control signal from the active state. for example, the time between rn and the ck of fd2 cell. if the release of the rn occurs too soon after the active edge of the clock, the state of the fd2 be- comes uncertain. the uncertainty can be caused by the value set by the rn or the value clocked into the fd2 from the data input. figure 1-12. removal time 1.5.2.6 minimum pulse widths figure 1-13. shows the definition of minimum pulse width. the minimum pulse width timing check is the minimum allowable time for the positive (high) or nega- tive (low) phase of each cycle. figure 1-13. minimum pulse width 1.5.2.7 minimum period figure 1-14. shows the definition of minimum period. the minimum period timing check is the minimum allowable time for one complete cycle of the signal. figure 1-14. minimum period rn ck t rm 50% 50% ck t pwh 50% t pwl ck 50% t prd 1.5 timings introduction std110 1-20 sec asic 1.5.3 temperature and supply voltage the next ?gure describes propagation delay derating factors (k t , k v ) as a function of on-chip junction temperature (t j ) and supply voltage (v dd ). as a result of power dissipation, the junction temperature is generally higher than the ambient temperature. the temperature of the die inside the package (junction temperature, t j ) is calculated using chip power dissipation and the thermal resistance to the ambient temperature ( q ja ) of the package. information on package thermal performance can be obtained from sec application engineers. figure 1-15. effect of temperature and supply voltage on propagation delay temperature (t j ) k t 1.086 1.065 1.000 0.964 0.906 C40 0 70 25 85 1.143 125 ( c) supply voltage (v dd ) 1.075 0.940 2.3 2.5 (volt) k v 1.000 2.7 introduction 1.5 timings sec asic 1-21 std110 1.5.4 best and worst case conditions a circuit should be designed to operate properly within a given speci?cation level, either commercial or industrial. it is recommended that circuits be simulated for best case, normal case, and worst case conditions at each speci?cation level. the following expressions also allow for the effect of process variation on circuit performance. best case(worst case): t bc (t wc ) = k p x k t x k v x t nom where t bc = best case propagation delay t wc = worst case propagation delay t nom = normal propagation delay ( t j = 25 o c, v dd = 2.5v and typical process) k p , k t , k v = refer totable 1-2., table 1-3., and table 1-4. 1.5.5 derating factors of std110 the multipliers can be applied to nominal delay data in order to estimate the effects of supply voltage, temperature and process. nominal data are provided for conditions of v dd = 2.5v, t j = 25 c and typical process. the derating factors of std110 is as follows. table 1-2. std110 cell process derating factor (k p ) table 1-3. std110 cell temperature derating factor (k t ) table 1-4. std110 cell voltage derating factor (k v ) process factor (k p ) slow typ fast 1.212 1.0 0.841 temp. ( o c) 125 85 70 25 0 C40 k t 1.143 1.086 1.065 1.000 0.964 0.906 voltage (v) 2.3 2.5 2.7 k v 1.075 1.000 0.940 1.6 delay model introduction std110 1-22 sec asic 1.6 delay model the asic timing characteristics consist of the following components: ? cell propagation delay from input to output transitions based on input waveform slope, fanout loads and distributed interconnection wire resistance and capacitance. ? interconnection wire delay across the metal lines. ? timing requirement parameters such as setup time, hold time, recovery time, skew time, minimum pulse width, etc. ? derating factors for junction temperature, power supply voltage, and process variations. timing model for std110 focuses on how to characterize cell propagation delay time accurately. to accomplish this goal, 2-dimensional table look-up delay model has been adopted. the index variables of this table are input waveform slope and output load capacitance. see the ?gure below. sec asic design automation system supports an n-dimensional table model even though we adopted 2-dimensional model for our 0.25 m m cell-based products. figure 1-16. 2-dimensional table delay model propagation delay [ns] input waveform slope [ns] load cap [pf] 1.5 1.0 0.5 1.0 2.0 3.0 0.4 0.8 1.2 introduction 1.6 delay model sec asic 1-23 std110 the table 1-5. shows an example of this model for 2-input nand cell. the data in this table are high-to-low transition delay times from one of the two input pins to output pin. the number of points and values of the index variables can differ for each cell. table 1-5. table delay model example notice that 4-by-4 table is used. delay values between grid points and beyond this table are determined by linear interpolation and extrapolation methods. this general table delay model provides great ?exibility as well as high accuracy since extensive software revisions are not required when a cell library is updated. the other timing components such as interconnection wire delay, timing requirement parameters and derating factors are characterized in a commonly-accepted way in industry. the ?gure below summarizes the features of sec asics delay model. 2-dimensional table delay model for output loading and input waveform slope effects is used.the slopes (t r , t f ) and delay times (t plh , t phl ) of all cell instances are calculated recursively. the input waveform slope of each primary input pad and the loading capacitance of each primary output pad can be assigned individually or by default. a pin to pin delays of cells and interconnection wires are supported. ? the effect of distributed interconnection wire resistance and capacitance on cell delay is analysed using the effective capacitance concept. figure 1-17. features of delay model slop \ cap 0.0050 0.0220 0.3030 0.5840 0.0200 0.03644 0.07275 0.66481 1.25660 0.1700 0.05508 0.09725 0.68658 1.27820 1.5850 0.07719 0.16698 0.92337 1.49790 3.0000 0.06421 0.17730 1.10970 1.74950 s1 s3 s2 co1 co2 co3 ck q d a_y b_y ? ? a 1.7 testability design methodology introduction std110 1-24 sec asic 1.7 testability design methodology 1.7.1 scan design ? multiplexed scan ?ip-?op that minimizes the area or delay overhead needed to implement scan design. ? automated design rules checking, scan insertion, and test pattern generation ? high fault coverage on synchronous designs 1.7.2 boundary-scan ? ieee std 1149.1 ? jtag boundary-scan registers with primitive cells ? boundary-scan description language (bsdl) description for board testing ? combination with internal scan design and core testing boundary scan architecture a boundary scan architecture contains tap (test access port), tap controller, instruction register and a group of test data registers. the instruction and test data registers are separate shift-register-based paths connected in parallel with a common serial data input and a common serial data output which are connected to tap, tdi and tdo signals. tap controller selects the alternative instruction and test data register paths between tdi and tdo. the schematic view of the top level design of the test logic architecture is shown in the figure 1- 18. figure 1-18. jtag test access port (tap) block diagram multiplexer scannable register device identity register bypass register instruction register ta p controller system logic boundary scan path tdi tms tck tdo test access port (tap) mux introduction 1.7 testability design methodology sec asic 1-25 std110 boundary scan functional block descriptions tap (test access port) tap is a general-purpose port that can provide with an access to many test support functions built into a component, including the test logic. it includes three inputs (tck; test clock signal, tms; test mode signal and tdi; test data input) and one output (tdo; test data output) required by the test logic. an optional fourth input (trstn; test reset) is provided for the asynchronous initialization of the test logic. the values applied at tms and tdi pins are sampled on the rising edge of tck, and the value placed on tdo pin changes on the falling edge of tck. tap controller tap controller receives tck, interprets the signals on tms, and generates clock and control signals for both instruction and test data registers and for other parts of the test circuitries as required. instruction register/instruction decoder test instructions are shifted into and held by the instruction register. test instructions include a selection of tests to be performed or the test data register to be accessed. a basic 3-bit instruction register and its instruction decoder are provided as macrofunctions in the library. test data registers data registers include a bypass register, a boundary scan register, a device identi?cation register and other design speci?c registers. only the bypass- and boundary scan registers are mandatory; the rest are optional. bypass register: the bypass register provides a single-bit serial connection through the circuit when none of the other test data registers is selected. it can be used to allow test data to ?ow through a given device to the other components in a product without affecting a normal operation. boundary scan register: the boundary scan register detects typical production defects in board interconnects, such as opens, shorts, etc. it also allows an access to component inputs and outputs when you test their logic or sample ?ow-through signals. special boundary scan register macrocells are provided for this purpose. these special registers is discussed in the next section of next pages. design-speci?c test data register: these optional registers may be provided to allow an access to design-speci?c test support features in the integrated circuit, such as self-test, scan test. device identi?cation register: this is an optional test data register that allows the manufacturer part number and variant of a components to be identi?ed. the 32-bit identi?cation register is partitioned into four ?elds: device version identi?er1st ?eld the ?rst four bits beginning from msb device part number 2nd ?eld 16 bits manufacturers jedec number 3rd ?eld 11 bits lsb 4th ?eld 1 bit tied in high 1.7 testability design methodology introduction std110 1-26 sec asic the asic designer is free to ?ll the version and part number in any manner as long as the total twenty bits are used. secs jedec code: 78 decimal = 1001110 continuation ?eld (4 bits) = 0000 contents of device identi?cation register: xxxx xxxxxxxxxxxxxxxx 0000 1001110 1 users can de?ne these two ?elds. 1.7.3 bist (built-in self-test) ? ef?cient test solution for compiled memory macrocells ? at speed and parallel testing of multiple memories ? less routing overhead and test pin requirements instruction register tap controller bypass register mux circuit prior to boundary scan (core logic) boundary scan register (connection of all boundary scan cells) boundary scan path i/o pad tdi tms tck tdo test access port (tap) test data register introduction 1.8 maximum fanouts sec asic 1-27 std110 1.8 maximum fanouts 1.8.1 internal macrocells the maximum fanouts for std110 primitive cells are as follows. note that these fanout limitation values are calculated when the rise and fall times of the input signal is 0.213ns. depending on the rise and fall times, the maximum fanout limitations can be varied case by case. in the following table the maximum fanout values for all pins of std110 internal macrocells are listed. table 1-6. maximum fanouts of internal macrocells (when input t r /t f = 0.213ns, one fanout (sl) = 0.006710pf ) cell name output pin maximum fanouts ad2 y 48 ad2d2 y 97 ad2d4 y 190 ad2dh y 21 ad3 y 48 ad3d2 y 94 ad3d4 y 188 ad3dh y 21 ad4 y 48 ad4d2 y 94 ad4d4 y 185 ad4dh y 21 ad5 y 23 ad5d2 y 46 ad5d4 y 190 ao21 y 22 ao211 y 14 ao2111 y 9 ao2111d2 y 97 ao211d2 y 28 ao211d2b y 97 ao211d4 y 195 ao211dh y 7 ao21d2 y 45 ao21d2b y 95 ao21d4 y 192 ao21dh y 10 ao22 y 22 ao221 y 13 ao221d2 y 95 ao221d4 y 192 ao222 y 13 ao2222 y 8 ao2222d2 y 95 ao2222d4 y 192 ao222a y 20 ao222d2 y 25 ao222d2a y 95 ao222d2b y 95 ao222d4 y 191 ao222d4a y 192 ao22a y 22 ao22d2 y 43 ao22d2a y 43 ao22d2b y 96 ao22d4 y 191 ao22d4a y 191 ao22dh y 9 ao22dha y 9 ao31 y 21 ao311 y 13 ao3111 y 8 ao3111d2 y 97 ao311d2 y 97 ao311d4 y 191 ao31d2 y 43 ao31d4 y 194 ao31dh y 9 ao32 y 20 ao321 y 12 ao321d2 y 95 ao321d4 y 192 ao322 y 11 ao322d2 y 95 ao322d4 y 192 ao32d2 y 97 ao32d4 y 191 ao33 y 19 ao331 y 11 ao331d2 y 95 ao331d4 y 193 ao332 y 10 ao332d2 y 95 ao332d4 y 192 ao33d2 y 95 ao33d4 y 190 ao4111 y 8 ao4111d2 y 95 busholder y 10000 dc4 y0 47 y1 47 y2 47 y3 47 dc4i yn0 43 yn1 43 yn2 44 yn3 44 dc8i yn0 30 yn1 30 yn2 30 yn3 30 yn4 30 yn5 30 yn6 30 yn7 30 dl1d2 y 96 dl1d4 y 195 dl2d2 y 97 dl2d4 y 197 dl3d2 y 96 dl3d4 y 194 dl4d2 y 95 dl4d4 y 194 dl5d2 y 96 dl5d4 y 194 dl10d2 y 96 dl10d4 y 194 cell name output pin maximum fanouts 1.8 maximum fanouts introduction std110 1-28 sec asic oak_duclk 10 ck 359 ckb 358 oak_duclk 16 ck 359 ckb 359 fa s 47 co 46 fad2 s 96 co 96 fadh s 20 co 20 fd1 q 47 qn 47 fd1d2 q 95 qn 95 fd1cs q 47 qn 47 fd1csd2 q 95 qn 95 fd1q q 48 fd1qd2 q 95 fd1s q 47 qn 47 fd1sd2 q 97 qn 95 fd1sq q 47 fd1sqd2 q 95 fd2 q 47 qn 48 fd2d2 q 95 qn 95 fd2cs q 48 qn 47 fd2csd2 q 97 qn 94 fd2q q 48 fd2qd2 q 95 fd2s q 46 qn 48 fd2sd2 q 95 qn 95 fd2sq q 47 fd2sqd2 q 95 fd3 q 48 qn 48 fd3d2 q 103 qn 103 fd3cs q 47 qn 48 fd3csd2 q 95 qn 94 fd3q q 47 fd3qd2 q 95 fd3s q 48 qn 48 fd3sd2 q 95 qn 95 fd3sq q 47 fd3sqd2 q 95 fd4 q 47 qn 48 fd4d2 q 95 qn 94 fd4cs q 46 qn 45 cell name output pin maximum fanouts fd4csd2 q 97 qn 91 fd4q q 47 fd4qd2 q 95 fd4s q 47 qn 46 fd4sd2 q 95 qn 94 fd4sq q 47 fd4sqd2 q 94 fd5 q 47 qn 47 fd5d2 q 95 qn 95 fd5s q 47 qn 47 fd5sd2 q 97 qn 95 fd6 q 47 qn 48 fd6d2 q 95 qn 95 fd6s q 46 qn 47 fd6sd2 q 95 qn 95 fd7 q 48 qn 48 fd7d2 q 95 qn 95 fd7s q 47 qn 48 fd7sd2 q 95 qn 95 fd8 q 47 qn 46 fd8d2 q 95 qn 94 fd8s q 48 qn 48 fd8sd2 q 95 qn 94 fds2 q 47 qn 46 fds2d2 q 95 qn 95 fds2cs q 47 qn 46 fds2csd2 q 95 qn 95 fds2s q 47 qn 48 fds2sd2 q 95 qn 95 fds3 q 47 qn 47 fds3d2 q 95 qn 95 fds3cs q 48 qn 47 fds3csd2 q 95 qn 95 fds3s q 46 qn 48 cell name output pin maximum fanouts introduction 1.8 maximum fanouts sec asic 1-29 std110 fds3sd2 q 95 qn 95 fj1 q 47 qn 48 fj1d2 q 95 qn 95 fj1s q 46 qn 48 fj1sd2 q 95 qn 95 fj2 q 46 qn 47 fj2d2 q 95 qn 95 fj2s q 46 qn 48 fj2sd2 q 95 qn 95 fj4 q 47 qn 47 fj4d2 q 94 qn 96 fj4s q 48 qn 47 fj4sd2 q 95 qn 93 ft2 q 48 qn 48 ft2d2 q 94 qn 94 ha s 47 co 47 had2 s 94 co 95 hadh s 21 co 21 iv y 48 ivcd11 y 46 yn 47 ivcd13 y 43 yn 144 ivcd22 y 94 yn 97 ivcd26 y 87 yn 284 ivcd44 y 191 yn 196 ivd2 y 97 ivd3 y 144 ivd4 y 195 ivd6 y 282 ivd8 y 381 ivd16 y 787 ivdh y 21 ivt y 41 ivtd2 y 89 ivtd4 y 187 ivtd8 y 373 ivtd16 y 756 ivtn y 41 ivtnd2 y 89 ivtnd4 y 187 ivtnd8 y 373 ivtnd16 y 757 cell name output pin maximum fanouts ld1 q 47 qn 46 ld1d2 q 95 qn 95 ld1a q 35 ld1d2a q 77 ld1q q 47 ld1qd2 q 95 ld2 q 46 qn 47 ld2d2 q 95 qn 95 ld2q q 47 ld2qd2 q 95 ld3 q 47 qn 47 ld3d2 q 95 qn 95 ld4 q 48 qn 46 ld4d2 q 97 qn 96 ld5 q 47 qn 47 ld5d2 q 95 qn 95 ld5q q 47 ld5qd2 q 95 ld6 q 46 qn 47 ld6d2 q 95 qn 95 ld6q q 47 ld6qd2 q 95 ld7 q 47 qn 47 ld7d2 q 95 qn 95 ld8 q 48 qn 47 ld8d2 q 97 qn 96 oak_ldi2 q 47 qn 47 oak_ldi2d2 q 95 qn 95 oak_ldi3 q 47 qn 47 oak_ldi3d2 q 95 qn 95 ls0 q 44 qn 44 ls0d2 q 88 qn 88 ls1 q 22 qn 22 ls1d2 q 95 qn 95 mx2 y 47 mx2d2 y 95 mx2d4 y 188 mx2dh y 21 mx2i yn 22 mx2ia yn 22 mx2id2 yn 95 cell name output pin maximum fanouts 1.8 maximum fanouts introduction std110 1-30 sec asic mx2id2a yn 95 mx2id4 yn 192 mx2id4a yn 191 mx2idh yn 9 mx2idha yn 9 mx2ix4 yn0 22 yn1 22 yn2 22 yn3 22 mx2x4 y0 48 y1 48 y2 48 y3 48 mx3i yn 46 mx3id2 yn 94 mx3id4 yn 190 mx4 y 46 mx4d2 y 92 mx4d4 y 177 mx8 y 46 mx8d2 y 90 mx8d4 y 170 nd2 y 45 nd2d2 y 91 nd2d4 y 182 nd2dh y 20 nd3 y 30 nd3d2 y 62 nd3d4 y 124 nd3dh y 14 nd4 y 23 nd4d2 y 46 nd4d2b y 94 nd4d4 y 191 nd4dh y 10 nd5 y 47 nd5d2 y 94 nd5d4 y 193 nd6 y 47 nd6d2 y 95 nd6d4 y 191 nd8 y 47 nd8d2 y 95 nd8d4 y 191 nid y 48 oak_nid10p y 2384 nid16 y 767 nid2 y 96 oak_nid20p y 4731 nid3 y 142 nid4 y 192 nid6 y 283 nid8 y 378 nidh y 20 nit y 42 nitd16 y 758 nitd2 y 89 nitd4 y 186 nitd8 y 373 nitn y 41 nitnd16 y 757 nitnd2 y 89 nitnd4 y 186 nitnd8 y 373 nr2 y 23 cell name output pin maximum fanouts nr2a y 47 nr2d2 y 47 nr2d2b y 96 nr2d4 y 194 nr2dh y 10 nr3 y 15 nr3a y 30 nr3d2 y 30 nr3d2b y 96 nr3d4 y 194 nr3dh y 9 nr4 y 48 nr4d2 y 97 nr4d4 y 195 nr4dh y 21 nr5 y 48 nr5d2 y 97 nr5d4 y 194 nr6 y 48 nr6d2 y 97 nr6d4 y 195 nr8 y 47 nr8d2 y 95 nr8d4 y 189 oa21 y 23 oa211 y 22 oa2111 y 21 oa2111d2 y 94 oa211d2 y 44 oa211d2b y 94 oa211d4 y 192 oa211dh y 10 oa21d2 y 46 oa21d2b y 95 oa21d4 y 191 oa21dh y 10 oa22 y 21 oa221 y 18 oa221d2 y 95 oa221d4 y 191 oa222 y 16 oa2222 y 11 oa2222d2 y 95 oa2222d4 y 192 oa222d2 y 32 oa222d2b y 96 oa222d4 y 192 oa22a y 23 oa22d2 y 42 oa22d2a y 47 oa22d2b y 96 oa22d4 y 192 oa22d4a y 192 oa22dh y 10 oa22dha y 10 oa31 y 14 oa311 y 14 oa3111 y 12 oa3111d2 y 95 oa311d2 y 94 oa311d4 y 191 oa31d2 y 28 oa31d4 y 191 oa31dh y 7 oa32 y 13 cell name output pin maximum fanouts introduction 1.8 maximum fanouts sec asic 1-31 std110 oa321 y 12 oa321d2 y 96 oa321d4 y 192 oa322 y 10 oa322d2 y 95 oa322d4 y 192 oa32d2 y 95 oa32d4 y 191 oa33 y 11 oa331 y 11 oa331d2 y 95 oa331d4 y 191 oa332 y 7 oa332d2 y 95 oa332d4 y 192 oa33d2 y 95 oa33d4 y 193 oa4111 y 8 oa4111d2 y 95 or2 y 47 or2d2 y 94 or2d4 y 190 or2dh y 21 or3 y 47 or3d2 y 97 or3d4 y 196 or3dh y 21 or4 y 43 or4d2 y 87 or4d4 y 191 or4dh y 21 or5 y 43 or5d2 y 86 or5d4 y 191 scg1 y 30 scg1d2 y 61 scg2 y 47 scg2d2 y 94 scg3 y 30 scg3d2 y 61 scg4 y 45 scg4d2 y 90 scg5 y 46 scg5d2 y 93 scg6 y 47 scg6d2 y 95 scg7 y 43 scg7d2 y 87 scg8 y 47 scg8d2 y 95 scg9 y 47 scg9d2 y 95 scg10 y 47 scg10d2 y 94 scg11 y 14 scg11d2 y 30 scg12 y 23 scg12d2 y 46 scg13 y 43 scg13d2 y 87 scg14 y 43 scg14d2 y 87 scg15 y 30 scg15d2 y 61 scg16 y 22 cell name output pin maximum fanouts scg16d2 y 45 scg17 y 44 scg17d2 y 90 scg18 y 30 scg18d2 y 61 scg19 y 22 scg19d2 y 44 scg20 y 23 scg20d2 y 47 scg21 y 14 scg21d2 y 30 scg22 y 22 scg22d2 y 46 scg23 s 47 co 46 scg23d2 s 94 co 93 xn2 y 48 xn2d2 y 95 xn2d4 y 191 xn3 y 47 xn3d2 y 93 xn3d4 y 176 xo2 y 47 xo2d2 y 94 xo2d4 y 191 xo3 y 47 xo3d2 y 94 xo3d4 y 180 cell name output pin maximum fanouts 1.8 maximum fanouts introduction std110 1-32 sec asic 1.8.2 i/o cells the maximum fanouts for i/o cells are as follows. table 1-7. maximum fanouts of i/o cells (t r /t f = 0.213ns, one fanout (sl) = 0.006710pf) cell name output pin maximum fanouts phic y 270 phicd y 270 phicu y 270 phis y 270 phisd y 270 phisu y 270 phit y 270 phitd y 270 phitu y 270 phsosck1 yn 191 phsosck17 yn 191 phsosck2 yn 193 phsosck27 yn 193 phsoscm1 yn 194 phsoscm16 yn 194 phsoscm2 yn 205 phsoscm26 yn 205 phsoscm3 yn 402 phsoscm36 yn 402 pic y 131 pic_abb y 131 picc_abb y 135 picd y 131 picen_abb y 130 picu y 131 pipci y 131 pis y 130 pisd y 130 pisu y 130 psosck1 yn 193 psosck2 yn 193 psoscm1 yn 71 psoscm2 yn 251 ptic y 270 pticd y 270 pticu y 270 ptipci y 270 ptis y 270 ptisd y 270 ptisu y 270 ptit y 270 ptitd y 270 ptitu y 270 introduction 1.8 maximum fanouts sec asic 1-33 std110 1.8.3 ck cell max fanout std110 maximum fanout for ck cells 1.9 package capability by lead count introduction std110 1-34 sec asic 1.9 package capability by lead count package lead inductance lead count sop/ssop (small outline package) 8 16 20 2428445670 3.9 x 8.7mm < 2nh n 3.9 x 9.9 mm < 4nh n 4.0 x 5.1mm < 2nh n 4.4 x 6.9 mm < 3nh n 4.4 x 6.9 mm < 3nh n 5.3 x 3.0 mm < 3nh n 5.3 x 7.2 mm < 3nh n 5.3 x 10.2 mm < 4nh n 5.3 x 15.6 mm < 5nh n 5.4 x 14.1 mm < 5nh n 7.5 x 18.4 mm < 8nh n 12.6 x 29.0mm < 20nh n 12.7 x 29.0 mm < 16nh n tsop/tssop (thin sop) 8 28 32 4448545666 4.4 x 3.0mm < 3nh n 4.4 x 9.7 mm < 3nh n 6.1 x 9.7mm < 3nh n 6.1 x 14.0 mm < 6nh n 10.2 x 18.9 mm < 8nh n 10.2 x 21.4 mm < 7nh n 10.2 x 22.6 mm < 7nh nn n 12.0 x 20.0mm < 6nh n 12.4 x 16.4 mm < 7nh n psop/pssop (power sop) 81620 3.9 x 9.9 mm < 3nh n 6.1 x 7.64 mm < 3nh n 7.6 x 12.8 mm < 3nh n 11.0 x 15.9 mm < 6nh n introduction 1.9 package capability by lead count sec asic 1-35 std110 package lead inductance lead count qfp (quad flat package) 44 48 64 80 100 128 160 208 240 256 7 x 7 mm < 3nh n 10 x 10 mm < 5nh nn 12 x 12 mm < 5nh n 14 x 14 mm < 6nh nn 14 x 20 mm < 12nh nnnn 24 x 24 mm < 11nh n 28 x 28 mm < 17nh nn n 32 x 32 mm < 15nh n tqfp (thin quad flat package) 32 48 80 100 144 160 176 208 7 x 7 mm < 4nh nn 12 x 12 mm < 5nh n 14 x 14 mm < 5nh n 14 x 20 mm < 10nh n 20 x 20 mm < 9nh n 24 x 24 mm < 11nh nn 28 x 28 mm < 13nh n plcc (plastic leaded chip carrier) 44 84 16.6 x 16.5mm <5nh n 29.3 x 29.3 mm < 13nh n package lead inductance lead count sbga (super bga) lp/g lsig 256 304 352 432 560 600 27 x 27 mm < 3nh < 7nh n 31 x 31 mm < 3nh < 8nh n 35 x 35 mm < 3nh < 8nh n 40 x 40 mm < 3nh < 9nh n 42.5 x 42.5 mm < 3nh < 9nh n 45 x 45 mm < 3nh < 9nh n pbga (plastic bga) lp/g lsig 119 121 169 204 208 217 225 249 256 272 300 14 x 22 mm < 4nh <9nh n 15 x 15 mm < 4nh < 13nh n 23 x 23 mm < 4nh < 18nh n nnn n 27 x 27 mm < 4nh < 21nh n nnn 31 x 31 mm < 4nh < 13nh 35 x 35 mm < 4nh < 14nh pbga (plastic bga) lp/g lsig 304 316 324 329 352 360 385 388 420 456 14 x 22 mm < 4nh <10nh 15 x 15 mm < 4nh < 13nh 23 x 23 mm < 4nh < 18nh 27 x 27 mm < 4nh < 21nh nn 31 x 31 mm < 4nh < 13nh nnnn 35 x 35 mm < 4nh < 14nh nnnn 1.10 power dissipation introduction std110 1-36 sec asic 1.10 power dissipation 1.10.1 estimation of power dissipation in cmos circuit cmos circuits have been traditionally considered to consume low power since they draw very small amount of current in a steady state. however, the recent revolution in a cmos technology that allows very high gate density has changed the way the power dissipation should be understood. the power dissipation in a cmos circuit is affected by various factors such as the number of gates, the switching frequency, the loading on the output of a gate, and so on. power dissipation is important when designers decide the amount of necessary power supply current for the device to operate in safety. propagation delays and reliability of the device also depend on power dissipation that determines the temperature at which the die operates. to obtain high speed and reliability, designers must estimate power dissipation of the device accurately and determine the appropriate environments including the package and system cooling methods. this section describes the concepts of two types of power dissipation (static and dynamic) in a cmos circuit, the method of calculating those in the sec std110 library. 1.10.2 static (dc) power dissipation there are two types of static or dc current contributing to the total static power dissipation in cmos circuits. one is the leakage current of the gates resulted by a reverse bias between a well and a substrate region. there is no dc current path from power to ground in a cmos because one of the transistor pair is always off, therefore, no static current except the leakage current ?ows through the internal gates of the device. the amount of this leakage current is, however, in the range of tens of nano amperes, which is negligible. the other is dc current that ?ows through the input and output buffers when the circuit is interfaced with other devices, especially ttl. the current of pull-up/ pull-down transistor in the input buffers is about 33 m a (at 3.3v) and 25ua (at 2.5v) typically, which is also negligible. therefore, only dc current that the output buffers source or sink has to be counted to estimate the total static power dissipation. dc power dissipation of output and bi-directional buffers is determined by the following formula: where, n = number of output and bidirectional buffers t = total operation time in output mode t h = the sum of logic high state time t l = the sum of logic low state time t l + t h = t (supposed that all output and bidirectional buffers have just logic high or low state) sout is the output mode ratio of bidirectional buffers (typically 0.5) p dc_output [mw] v ol k () i ol k () t lk () () k1 = n ? v dd v oh k () C () i oh k () t hk () () k1 = n ? + ? ? ?? t = p dc_bi [mw] v ol k () i ol k () t lk () () k1 = n ? v dd v oh k () C () i oh k () t hk () () k1 = n ? + ? ? ?? s out t = introduction 1.10 power dissipation sec asic 1-37 std110 1.10.3 dynamic (ac) power dissipation when a cmos gate changes its state, it draws switching current as a result of charging or discharging a load capacitance, c l . the energy associated with the switching current for a node capacitance, c l , is where v dd is the power supply voltage. in addition to the power dissipated by the load capacitance, cmos circuits consume power due to the short- circuit current ?owing through a temporary v dd -to-ground path during switching. the dynamic power dissipation for an entire chip is much more complicated to estimate since it depends on the degree of switching activity of the circuit. sec has found that the degree of switching activity is 10% on the average and recommends this number to be used in estimating the total dynamic power dissipation. 1.10.4 power dissipation in std110 this section describes the equations on how to estimate the power dissipation in std110. as explained in the previous section, the total power dissipation (p total ) consists of static power dissipation (p dc ) and dynamic power dissipation (p ac ). p total = p ac + p dc p dc is negligible in case of cmos logic. the dynamic power dissipation is caused by three components: input buffers (p ac_input ), output buffers (p ac_output ), bidirectional buffers (p ac_bi ), and internal cells (p ac_internal ). p ac = p ac_ input + p ac_output + p ac_bi + p ac_internal each term mentioned above is characterized by the following equations: c l v dd 2 p ac_input [mw] 2.5 i j_eq_p f j 100 --------- - s j ? ?? 3.3 + j n_2.5v_input ? i k_eq_p f k 100 --------- - s k ? ?? 6.25 + k n_3.3v_input ? 0.001 s i f i c i_inload () i n_total_input ? = p ac_output [mw] 2.5 i i_eq_p f i 100 --------- - s i ? ?? 3.3 + i n_2.5v_output ? i j_eq_p f j 100 --------- - s j ? ?? j n_3.3v_output ? + = 6.25 0.001 s i f i c i_outload () 10.89 0.001 s j f j c j_outload () j n_3.3v_output ? + i n_2.5v_output ? p ac_bi [mw] p ac_bi_input 1s out C () p ac_bi_output s out + = p ac_bi_input [mw] 2.5 i j_eq_p f j 100 --------- - s j ? ?? j n_2.5v_bi ? 3.3 i k_eq_p f k 100 --------- - s k ? ?? 6.25 + k n_3.3v_bi ? 0.001 s i f i c i_inload () i n_total_bi ? + = p ac_bi_output [mw] 2.5 i i_eq_p f i 100 --------- - s i ? ?? i n_2.5v_bi ? 3.3 i j_eq_p f j 100 --------- - s j ? ?? + j n_3.3v_bi ? + = 6.25 0.001 s i f i c i_outload () i n_2.5v_bi ? 10.89 0.001 s i f i c i_outload () j n_3.3v_bi ? + p ac_internal [mw] 0.001 0.2317 s 0.0167 + () g f 0.001 p i f i () j n_macro ? + = 1.10 power dissipation introduction std110 1-38 sec asic where n_2.5v_input is the number of 2.5v interface input buffers used n_3.3v input is the number of 3.3v interface input buffers used, n_total_input = n_2.5v_input + n_3.3v input n_2.5v_output is the number of 2.5v interface output buffers used, n_3.3v_output is the number of 3.3v interface output buffers used, n_2.5v_bi is the number of 2.5v interface bidirectional buffers used, n_3.3v_bi is the number of 3.3v interface bidirectional buffer used, n_macro is the number of macro cells used, g is the size of the design in gate count, f is the operating frequency in mhz, s is the estimated degree of switching activity (typically 0.1 for internal and 0.5 for i/o), sout is the output mode ratio of bidirectional buffers (typically 0.5), c is the load capacitance in pf. p is the characterized power for the i-th hard macro block ( m w/mhz) 1.10.5 temperature and power dissipation the total power dissipation, p total can be used to ?nd out the device temperature by the following equation: q ja = (t j C t a ) / p total where q ja is the thermal impedance, t j is the junction temperature of the device, t a is the ambient temperature. thermal impedances of the sec packages are given in the following table. the junction temperature, obtained by multiplying p total by the appropriate q ja and adding t a , determines the derating factor for the propagation delays and also indicates the reliability measures. hence, designers can achieve the desired derating factor and reliability targets by choosing appropriate packages and system cooling methods. table 1-10. thermal impedances of sec plastic packages sop/tsop pin number 20 24 28 32 44 50 54 62 66 q ja [ c/w] 63 58 41-44 46-56 44-71 39-59 34-56 27-33 34-46 qfp pin number 44 48 80 100 120 128 160 208 240 256 q ja [ c/w] 51-62 43-56 43-74 27-61 33-47 43-51 29-51 22-43 28-47 29-42 tqfp/lqfp pin number 32 64 100 144 160 176 208 256 q ja [ c/w] 68-70 47 37-70 38 35-62 31-34 37-56 30-42 pbga pin number 272 388 356 (tepbga) 452 (tepbga) q ja [ c/w] 19-22 16-19 16 14 sbga pin number 256 304 352 432 600 q ja [ c/w] 14.1 13.1 11.7 10.2 8.3 introduction 1.11 vdd/vss rules and guidelines sec asic 1-39 std110 1.11 v dd /v ss rules and guidelines there are three kinds of vdd and vss in std110, providing power to internal and i/o area. ? core logic C vdd2i, vss2i ? pre-driver (i/o area) C vdd2p, vdd3p, vss2p, vss3p ? output-drive (i/o area) C vdd2o, vdd3o, vss2o, vss3o the number of vdd and vss pads required for a speci?c design depends on the following factors: ? number of input and output buffers ? number of simultaneous switching outputs ? number of used gates and simultaneous switching gates ? operating frequency 1.11.1 basic placement guidelines the purpose of these guidelines is to minimize ir drop and noise for reliable device operations. ? core logic and pre-driver v dd /v ss pads should be evenly distributed on all sides of the chip. ? if you have core block demanding high power (compiled memory, analog), extra power pads should be placed on that side. ? power pads for sso group should be evenly distributed in the sso group. ? do not place the quiet signal (analog, reference) or analog power (vdda/ vssa) or bi-directional buffer next to a sso group. ? the opposite types of power pads (v dd /v ss ) should be placed as close as possible. ? if it is possible, do not place power pads (v dd /v ss ) at the corner of the chip. 1.11.2 vdd2i/vss2i allocation guidelines the purpose of these guidelines is to ensure that the minimum number of core logic power pad pairs meeting the electromigration current limit are used. the number of vdd2i/vss2i pads required for a speci?c design is determined by the function of the operating frequency of a chip. ? vdd2i bus width and the number of pads are equal to those of vss2i ? vdd2i/vss2i buses and pads should be distributed evenly in the core and on each side of the chip. ? the total number of core logic vdd2i pads is equal to that of vss2i pads. 1.11 vdd/vss rules and guidelines introduction std110 1-40 sec asic the number of vdd2i/vss2i pad pairs required for a design can be calculated from the following expression: the number of vdd2i/vss2i pad pairs = where, g = the core (excluding hard macro blocks) size in the gate counts s = the switching ratio (typically = 0.1) f = operating frequency (mhz) pi = characterized current for the i-th hard macro block (ma/mhz) fi = operating frequency for the i-th hard macro block (mhz) i em = current limit per vdd/vss pad pairs based on electromigration rule (80ma) for reliable device operation and minimize ir voltage drop, minimum number of vdd2i/vss2i power pad pairs is 4. extra power may be needed for the demanding high power macro blocks (sram, analog block...). 1.11.3 vdd2p/vss2p (vdd3p/vss3p) allocation guidelines. these guidelines ensure that an adequate input threshold voltage margin is maintained during a switching. the number of vdd2p/vss2p (vdd3p/vss3p) pads required for a design can be calculated from the following expression: in above expression, i eq_p = ? (average current of input/output buffers and bi-direction pre-drivers at maximum operational i/o frequency) [ma] (refer table 1-11) table 1-11. 2.5v interface input buffer type cmos cmos schmitt ieq_p (ma) 0.35 0.36 output pre-driver type driver tristate b1C4 b6C8 b10C12 t1C4 t6C8 t10C12 ieq_p (ma) normal 0.14 0.27 0.41 0.24 0.36 0.53 slew rate 0.14 0.25 0.35 0.25 0.35 0.45 0.001 0.0927 s 0.0067 + () gf pi fi () i n_macro ? + l em round up C number_ of_vdd2p/vss2p(vdd3p/vss3p) pairs l eq_p l em ---------- - round up C = where n_input is the number of input buffers used, n_output is the number of output buffers used, n_bi is the number of bi-directional buffers used, f is the operating frequency in mhz, s out is the output mode ratio of bi-directional buffers (typically 0.5), i em = current limit per vdd/vss pad pairs based on electromigration rule. (80ma) i eq_p i eq_p_in f i 100 --------- - ? ?? i n_input ? i j_eq_p_out f j 100 --------- - ? ?? j n_output ? i k_eq_p_in f k 100 --------- - ? ?? 1s out C () k n_bi ? i k_eq_p_out f k 100 --------- - ? ?? s out ++ + = introduction 1.11 vdd/vss rules and guidelines sec asic 1-41 std110 table 1-12. 3.3v interface for reliable device operation and minimum ir voltage drop, at least 4 pairs of vdd2p/vss2p (vdd3p/vss3p) power pads are needed. 1.11.4 vdd2o/vss2o (vdd3o/vss3o) allocation guide sso (simultaneous switching output) current induced in power and ground inductance can cause system failure because of voltage fluctuations. for the calculation of output drive power pad numbers, we consider the sso noise as well as the current limit based on electromigration. we may define the sso as outputs switching simultaneously in 1ns windows, such as bus type buffers. note: in case of heavy load, high frequency and low package inductance, the number of power pads for sso block could be determined by electromigration rule rather than limit of sso noise. so the number of power pads for sso block should be determined as the worse one of the power pad number under the limit of sso noise and that under the limit of electromigration rule. 1) number of power pads for sso block - number of power pads for sso block under the limit of sso noise ? calculating the number of power pad for each sso group from the following expressions: in above formula, nvddo each_sso = number of vdd2o (vdd3o) pad required for each sso group nvsso each_sso = number of vss2o (vss3o) pad required for each sso group nbvdd =number of buffers per vdd2o (vdd3o) power pad with 1nh lead inductance nbvss = number of buffers per vss2o (vss3o) ground pas with 1nh lead inductance l pg = package lead frame inductance (refer to 1.9 package capability by lead count) d sso_mode = d l_mode d p_mode d v_mode d t_mode d c_mode (refer to table 1-13. and table 1-14.) d l_mode = lead inductance derating factor d p_mode = process derating factor d v_mode = voltage derating factor d t_mode = temperature derating factor d c_mode = cload derating factor (*mode is either vdd or vss.) input buffer type cmos ttl schmitt trigger ieq_p (ma) normal 0.52 0.54 0.54 tolerant 0.60 0.60 0.51 output pre-driver type cmos driver tristate b1C4 b6C8 b10C12 t1C4 t6C8 t10C12 ieq_p (ma) normal normal 0.25 0.46 0.55 0.34 0.51 0.60 slew rate 0.28 0.37 0.46 0.36 0.45 0.55 tolerant --- (t1,2,3) 0.50 -- nvddo each_sso number_of_sso nbvdd ---------------------------------------------- l pg 1 d sso_mode -------------------------- = nvsso each_sso number_of_sso nbvss ---------------------------------------------- l pg 1 d sso_mode -------------------------- = 1.11 vdd/vss rules and guidelines introduction std110 1-42 sec asic table 1-13. derating equation (external 2.5v interface) table 1-14. derating equation (external 3.3v interface) item mode equation range package lead d l_vdd 0.0417 x lpg + 0.9375 0.0417 x lpg + 0.9375 3nh lpg 10nh 10nh lpg 15nh d l_vss 0.0417 x lpg + 0.9375 0.0417 x lpg + 0.9375 3nh lpg 10nh 10nh < lpg 15nh process d p_vdd 1.0000 1.2549 1.7255 best typical worst d p_vss 1.0000 1.2549 1.7451 best typical worst voltage d v_vdd C 0.8824 x voltage + 3.3235 C 0.5882 x voltage + 2.5882 2.3 voltage 2.5 2.5 < voltage 2.7 d v_vss C 0.8824 x voltage + 3.3235 C 0.5882 x voltage + 2.5882 2.3 voltage 2.5 2.5 < voltage 2.7 temperature d t_vdd 0.0024 x temperature + 1.0000 0.0032 x temperature + 0.9786 -40 temperature 25 25 < temperature 125 d t_vss 0.0031 x temperature + 1.0000 0.0029 x temperature + 1.0071 -40 temperature 25 25 < temperature 125 cload d c_vdd 0.0347 x cload + 0.6525 0.0286 x cload + 0.8369 10pf cload 30pf 30pf < cload 50pf d c_vss 0.0354 x cload + 0.6456 0.0285 x cload + 0.8544 10pf cload 30pf 30pf < cload 50pf item mode equation range package lead d l_vdd 0.0462 x lpg + 1.1538 0.0231 x lpg + 1.3846 3nh lpg 10nh 10nh lpg 15nh d l_vss 0.0469 x lpg + 0.7813 0.0313 x lpg + 0.9375 3nh lpg 10nh 10nh < lpg 15nh process d p_vdd 1.0000 1.2537 2.2985 best typical worst d p_vss 1.0000 1.1563 1.4063 best typical worst voltage d v_vdd C 1.2936 x voltage + 5.4328 C 0.4478 x voltage + 2.6119 3.0 voltage 3.3 3.3 < voltage 3.6 d v_vss C 0.4166 x voltage + 2.5000 C 0.4166 x voltage + 2.5000 3.0 voltage 3.3 3.3 < voltage 3.6 temperature d t_vdd 0.0036 x temperature + 1.0000 0.0041 x temperature + 0.9878 -40 temperature 25 25 < temperature 125 d t_vss 0.0038 x temperature + 1.0000 0.0028 x temperature + 1.0227 -40 temperature 25 25 < temperature 125 cload d c_vdd 0.0338 x cload + 0.6618 0.0554 x cload + 0.0146 10pf cload 30pf 30pf < cload 50pf d c_vss 0.0444 x cload + 0.5556 0.0370 x cload + 0.7778 10pf cload 30pf 30pf < cload 50pf introduction 1.11 vdd/vss rules and guidelines sec asic 1-43 std110 table 1-15. nbvdd/nbvss parameter (process = best, volt =2.7v/3.6v temp. = 0?c, llead = 1nh) note : pob1 means 1ma output driver cell, and pob12 means 12ma output driver cell. ? calculating the number of required power pad for total sso from the following expression: nvddo1sso = ? nvddoeach_sso nvsso1sso = ? nvssoeach_sso in the above formula, nvddosso = number of vdd2o (vdd3o) pad per total sso buffers nvssosso = number of vss2o (vss3o) pad per total sso buffers buffer type voltage type normal slew-rate medium (sm) slew-rate high (sh) nbvdd nbvss nbvdd nbvss nbvdd nbvss pob1 (pot1) 2.5v interface 176 178 C C C C pob2 (pot2) 140 142 C C C C pob4 (pot4) 102 102 160 160 C C pob6 (pot6) 84 84 142 142 C C pob8 (pot8) 72 72 116 116 C C pob12 (pot12) 60 60 96 96 236 236 phob1 (phot1) 3.3v interface 382 166 C C C C phob2 (phot2) 276 104 C C C C phob4 (phot4) 134 64 168 104 C C phob6 (phot6) 108 44 132 90 C C phob8 (phot8) 98 38 118 86 C C phob12 (phot12) 86 32 92 62 130 124 ptot1 5v tolerant 434 376 C ptot2 272 180 ptot3 203 116 1.11 vdd/vss rules and guidelines introduction std110 1-44 sec asic - number of power pads for sso block under the limit of electromigration rule ? calculating the following expression: 2) number of power pads for non-sso block ? calculating the following expression: 3) total number of power pads for vdd2o/vss2o (vdd3o/vss3o) ? calculating the following expressions: when open drain type buffers are used, you can consider using vss2o (vss3o) pads since they have current sink only. nvddo2 sso nvsso2 sso i eq_o i em ---------- - = where n_sso_output is the number of simultaneous switching output buffers used, n_sso_bi is the number of simultaneous switching bi-directional buffers used, c outload = output load capacitance [pf] v = operating voltage [v] f = maximum i/o operating frequency [mhz] s = switching ratio (typically 0.5) s out = output mode ratio of bidirectional buffers (typically 0.5) i em = current limit per vdd/vss pad paris based on electromigration rule. (80ma) i eq_o 0.001 c i_outload v i f i s i () i n_sso_output ? 0.001 c j_outload v j f j s j s j_out () j n_sso_bi ? + = nvddo non_sso nvsso non_sso i eq_o i em ---------- - = where n_non_sso_output is the number of non-simultaneous switching output buffers used, n_non_sso_bi is the number of non-simultaneous switching bi-directional buffers used, c outload = output load capacitance [pf] v = operating voltage [v] f = maximum i/o operating frequency [mhz] s = switching ratio (typically 0.5) s out = output mode ratio of bidirectional buffers (typically 0.5) i em = current limit per vdd/vss pad paris based on electromigration rule. (80ma) i eq_o 0.001 c i_outload v i f i s i () i n_non_sso_output ? 0.001 c j_outload v j f j s j s j_out () j n_non_sso_bi ? + = number of vdd2o (vdd3o) max nvddo1 sso nvddo2 sso , () nvddo non_sso + round-up = number of vss2o (vss3o) max n vsso1 sso nvsso2 sso , () nvsso non_sso + round-up = introduction 1.12 crystal oscillator consideration sec asic 1-45 std110 1.12 crystal oscillator consideration 1.12.1 overview std110 contains a circuit commonly referred to as an on-chip oscillator. the on-chip circuit itself is not an oscillator but an ampli?er which is suitable for being used as the ampli?er part of a feedback oscillator. with proper selection of off- chip components, this oscillator circuit performs better than any other types of clock oscillators. it is very important to select suitable off-chip components to work with the on- chip oscillator circuitry. it should be noted, however, that sec cannot assume the responsibility of writing speci?cations for the off-chip components of the complete oscillator circuit, nor of guaranteeing the performance of the ?nished design in production, any more than a transistor manufacturer, whose data sheets show a number of suggested ampli?er circuits, can assume responsibility for the operation, in production, of any of them. we are often asked why we dont publish a list of required crystal or ceramic resonator speci?cations, and recommend values for the other off-chip components. this has been done in the past, but sometimes with consequences that were not intended. suppose we suggest a maximum crystal resistance of 30ohms for some given frequency. then your crystal supplier tells you the 30ohm crystals are going to cost twice as much as 50ohm crystals. fearing that sec will not guarantee operation with 50ohm crystals, you order the expensive ones. in fact, sec guarantees only what is embodied within an sec product. besides, there is no reason why 50ohm crystals couldnt be used, if the other off-chip components are suitably adjusted. should we recommend values for the other off-chip components? should we do for 50ohm crystals or 30ohm crystals? with respect to what should we optimize their selection? should we minimize start-up time or maximize frequency stability? in many applications, neither start-up time nor frequency stability is particularly critical, and our recommendations are only restricting your system to unnecessary tolerances. it all depends on the application. 1.12.2 oscillator design considerations asic designers have a number of options for clocking the system. the main decision is whether to use the on-chip oscillator or an external oscillator. if the choice is to use the on-chip oscillator, what kinds of external components are to use an external oscillator, what type of oscillator would it be? the decisions have to be based on both economic and technical requirements. in this section we will discuss some of the factors that should be considered. 1.12 crystal oscillator consideration introduction std110 1-46 sec asic 1.12.2.1 on-chip oscillator in most cases, the on-chip ampli?er with the appropriate external components provides the most economical solution to the clocking problem. exceptions may arise in server environments when frequency tolerances are tighter than about 0.01%. the external components that commonly used for cmos gate oscillator are a positive reactance (normal crystal oscillator), two capacitors, c1 and c2, and two resistor rf and rx as shown in the ?gure below. figure 1-19. cmos oscillator 1.12.2.2 crystal speci?cations speci?cations for an appropriate crystal are not very critical, unless the frequency is. any fundamental-mode crystal of medium or better quality can be used. we are often asked what maximum crystal resistance should be speci?ed. the best answer to that question is the lower the better, but use what is available. the crystal resistance will have some effect on start-up time and steady-state amplitude, but not so much that it cant be compensated for by appropriate selection of the capacitance, c1 and c2. similar questions are asked about speci?cations of load capacitance and shunt capacitance. the best advice we can give is to understand what these parameters mean and how they affect the operation of the circuit (that being the purpose of this application note), and then to decide for yourself if such speci?cations are meaningful in your frequency tolerances are tighter than about 0.1%. part of the problem is that crystal manufacturers are accustomed to talking ppm tolerances with radio engineers and simply wont take your order until youve ?lled out their list of frequency tolerance requirements, both for yourself and to the crystal manufacturer. dont pay for 0.003% crystals if your actual frequency tolerance is 1%. c1 c2 rx rf pada pady feedback inside of a chip amplifier introduction 1.12 crystal oscillator consideration sec asic 1-47 std110 1.12.2.3 oscillation frequency the oscillation frequency is determined 99.5% by the crystal and up to about 0.5% by the circuit external to the crystal. the on-chip ampli?er has little effect on the frequency, which is as it should be, since the ampli?er parameterizes temperature and process dependent. the in?uence of the on-chip ampli?er on the frequency is by means of its input and output (pin-to-ground) capacitances, which parallel c1 and c2, and the pada-to-pady (pin-to-pin) capacitance, which parallels the crystal. the input and pin-to-pin capacitances are about 7pf each. internal phase deviations capacitance of 25 to 30pf. these deviations from the ideal have less effect in the positive reactance oscillator (with the inverting ampli?er) than in a comparable series resonant oscillator (with the non-inverting ampli?er) for two reasons: ?rst, the effect of the output capacitor; second, the positive reactance oscillator is less sensitive, frequency-wise, to such phase errors. 1.12.2.4 c1 / c2 selection optimal values for the capacitors c1 and c2 depend on whether a quartz crystal or ceramic resonator is being used, and also on application-speci?c requirements on start-up time and frequency tolerance. start-up time is sometimes more critical in microcontroller systems than frequency stability, because of various reset and initialization requirements. less commonly, accuracy of the oscillator frequency is also critical, for example, when the oscillator is being used as a time base. as a general rule, fast start-up and stable frequency tend to pull the oscillator design in opposite directions. considerations of both start-up time and frequency stability over temperature suggest that c1 and c2 should be about equal and at least 15pf. (but they dont have to be either.) increasing the value of these capacitances above some 40 or 50pf improves frequency stability. it also tends to increase the start-up time. these is a maximum value (several hundred ph, depending on the value of r1 of the quartz or ceramic resonator) above which the oscillator wont start up at all. if the on-chip ampli?er is a simple inverter, the user can select values for c1 and c2 between some 15 and 50pf, depending on whether start-up time or frequency stability is the more critical parameter in a speci?c application. 1.12.2.5 rf / rx selection a cmos inverter might work better in this application since a large rf (1mega- ohm) can be used to hold the inverter in its linear region. logic gates tend to have a fairly low output resistance, which testabilizes the oscillator. for that reason a resistor rx (several k-ohm) is often added to the feedback network, as shown in figure 1-19. at higher frequencies a 20 or 30pf capacitor is sometimes used in the rx position, to compensate for some of the internal propagation delay. 1.12 crystal oscillator consideration introduction std110 1-48 sec asic 1.12.2.6 pin capacitance rf / rx selection internal pin-to-ground and pin-to-pin capacitances, and pada and pady have some effect on the oscillator. these capacitances are normally taken to be in the range of 5 to 10pf, but they are extremely dif?cult to evaluate. any measurement of one such capacitance necessarily include effects from the others. one advantage of the positive reactance oscillator is that the pin-to ground cap. is paralleled by an external bulk capacitance, so a precise determination of their value is unnecessary. we would suggest that there is little justi?cation for more precision than to assign them a value of 7pf (pada-to-ground and pada-to-pady). this value is probably not in error by more than 3 or 4pf. the pady-to-ground cap. is not entirely a pin capacitance, but more like an equivalent output capacitance of some 25 to 30pf, having to include the effect of internal phase delays. this value varies to some extent with temperature, process, and frequency. 1.12.2.7 placement of components noise glitches arising at pada or pady pins at the wrong time can cause a miscount in the internal clock-generating circuitry. these kinds of glitches can be produced through capacitive coupling between the oscillator components and pcb traces carrying digital signals with fast rise and fall times. for this reason, the oscillator components should be mounted close to the chip and have short, direct traces to the pada, pady, and v ss pins. if possible, use dedicated v ss and v dd pin for only crystal feedback ampli?er. 1.12.3 troubleshooting oscillator problems the ?rst thing to consider in case of dif?culty is that there may be signi?cant differences in stray caps between the test jig and the actual application, particularly if the actual application is on a multi-layer board. noise glitches, that are not present in the test jig but are in the application board, are another possibility. capacitive coupling between the oscillator circuitry and other signal has already been mentioned as a source of miscounts in the internal clocking circuitry. inductive coupling is also doubtful, if there is strong current nearby. these problems are a function of the pcb layout. surrounding oscillator components with quit traces (for example, vcc and ground) will alleviate capacitive coupling to signals having fast transition time. to minimize inductive coupling, the pcb layout should minimize the areas of the loops formed by oscillator components. the loops demanding to be checked are as follows: pada through the resonator to pady; pada through c1 to the v ss pin; pady through c2 to the v ss pin. it is not unusual to ?nd that the ground ends of c1 and c2 eventually connect up to the v ss pin only after looping around the farthest ends of the board. not good. finally, it should not be overlooked that software problems sometimes imitate the symptoms of a slow-starting oscillator or incorrect frequency. never underestimate the perversity of a software problem. |
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